The present invention relates to a semiconductor device and a manufacturing technology thereof. More particularly, it relates to a technology effectively applicable to a semiconductor device having a metal formed by a plating method under a bump electrode, and a manufacturing method thereof.
As compared with wire bonding for establishing an electrical connection between the bonding pad portion on the surface of an IC (Integrated Circuit) chip and the lead of a package by a thin gold wire or the like, wireless bonding has been more developed for commercial use as a package enabling reductions in size and thickness.
The wireless bonding denotes a mounting style for establishing a connection with a bump formed on a bonding pad portion of an IC chip without using a bonding wire such as a thin gold wire when the IC chip is mounted on a printed board, or the like.
In particular, the CSP (chip size package) is the generic name of a package equal in size to or slightly larger than the semiconductor chip. With the CSP, (1) higher pin count becomes easier to achieve; and (2) a wide space between bump electrodes can be allowed, and further, the diameter of each bump electrode can be increased. For the reasons (1) and (2), and the like, the CSPs include the package in which bump electrodes for constituting external connection terminals are area-arrayed at the central part of the chip (of a so-called area array structure).
For manufacturing the IC of the area array structure, for example, a wiring for establishing a connection between the pad portions arrayed along the peripheral portion of a chip and bump electrodes arrayed on the entire surface of the chip, i.e., a so-called rewiring becomes necessary.
For example, Japanese Laid-Open Patent Publication No.Hei 2000-294607 discloses the following technology: In an insulating layer 6 made of a polyimide-based resin, an opening 6A for exposing the surface of an electrode pad portion 2A is formed. On the insulating film 6 including the inside of the opening 6A, a wiring 7 composed of, for example, a copper (Cu) film is formed. Further, on the wiring 7, an insulating layer 8 is formed. An opening 8B for exposing the one end side of the wiring 7 is formed in the insulating layer 8. Then, on the opening 8B, an electrode pad portion 9B is formed at a larger array pitch than the array pitch for the electrode pad portion 2A.